The present invention is generally related to CML I/O driver and receiver circuits, and more particularly to high-speed serial links required to operate from multiple voltages at either end of the high-speed link.
High-speed serial links are typically used for chip-to-chip and board-to-board communications. One particular type of high-speed serial link is known as a CML differential data link including a requisite output driver at the transmitter, and a corresponding differential receiver.
In some current applications, there is a need that the output driver circuit and receiver circuit be capable of operating from multiple voltage levels, such as 1.8 volts and 3.3 volts due to legacy constraints. Thus, there is a desire that the transmitter be operable to operate from multiple voltages, as well as the receiver front-end, preferably under software control.
The present invention achieves technical advantages as a programmable voltage termination circuit for a high-speed serial link, such as a CML serial link, that has software controlled termination voltages allowing both a transmitter and a receiver front-end to operate from multiple voltages under software control.
The present invention includes a programmable termination circuit adapted for use in both a transmitter and a receiver front-end that selectively couples one of several available terminating voltages to the respective circuit. The programmable termination circuit includes a combination of NMOS and PMOS FET""s, selectively coupling the desired termination voltage to the circuit upon software control, such as using a termination select signal. A level shift circuit is utilized to voltage shift this termination signal to be operable at the higher voltage level. A plurality of control signals are provided as outputs from the level shifter circuit and are used in gate control circuitry of the programmable termination circuit.
A back gate control circuit is further provided to address the possibility that one of the voltage supplies may come online before the other. This back gate control circuit controls PMOS switch devices of the programmable termination circuit so that there is no forward bias diode leakage during power up. The back gate control circuit ensures that the PMOS back gates are tied to the highest supply available at any instant to avoid forward biasing the diodes. The gates of the PMOS devices have additional control circuitry insuring that the gates are tied to the back gates if the higher supply voltage is power down, advantageously leading to a high impedance termination and shutting off the respective driver/receiver.